CMOS image sensor

A CMOS image sensor 101 comprises an active layer 11 of a first conductivity type arranged to be reversed biased and a pixel 20 comprising a photosensitive element comprising a well 22 of a second conductivity type and a well 21 of the first conductivity type containing active CMOS elements for reading and resetting the photosensitive element. The CMOS image sensor further comprises a doped buried layer 111 of the second conductivity type in the active layer beneath the well of the first conductivity type. The buried layer is arranged to extend a depletion region below the well of the second conductivity type also below the well of the first conductivity type

Image Sensor

A CCD image sensor of the type for providing charge multiplication by impact ionisation has an image area and a plurality of pixels. A separate multiplication register has a plurality of multiplication elements arranged to receive charge from the pixels of the image area. Each multiplication element comprises a sequence of electrodes operable to cause multiplication, the electrodes of each multiplication element being adjacent one another and non-overlapping. The non-overlapping arrangement may be manufactured by a CMOS process thereby providing a CCD image sensor with the advantages of CCD multiplication but using a CMOS manufacturing process

Image Sensor

An image sensor of the type for providing charge multiplication by impact ionisation has plurality of multiplication elements. Each element is arranged to receive charge from photosensitive elements of an image area and each element comprises a sequence of electrodes to move charge along a transport path. Each of the electrodes has an edge defining a boundary with a first electrode, a maximum width across the charge transport path and a leading edge that defines a boundary with a second electrode, the leading edge having one or more changes of direction so that the length of the edge is greater than the maximum width of the charge multiplication electrode across the charge transport path. Various arrangements with such changes of direction are provided including a zigzag saw-tooth arrangement, a castellated arrangement and a triangular arrangement

Electron Multiplying Low-Voltage CCD With Increased Gain

Novel designs for the gain elements in electron multiplying (EM) CCDs have been implemented in a device manufactured in a low voltage CMOS process. Derived with help from TCAD simulations, the designs employ modified gate geometries in order to significantly increase the EM gain over traditional structures. Two new EM elements have been demonstrated with an order of magnitude higher gain than the typical rectangular gate designs, achieved over 100 amplifying stages and without an increase in the electric field. The principles presented in this work can be used in CMOS and CCD imagers employing electron multiplication in order to boost the gain and reduce undesirable effects such as clock-induced charge generation and gain ageing

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths

Fully Depleted, Monolithic Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias

A new pixel design using pinned photodiode (PPD) in a 180 nm CMOS image sensor (CIS) process has been developed as a proof of principle. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the in-pixel p-wells have been added to the manufacturing process in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The new design exhibits nearly identical electro-optical performance under reverse bias as the reference PPD pixel it is based on, and the leakage current is effectively suppressed. The characterisation results from both front- and back-side illuminated sensor variants show that the epitaxial layer is fully depleted

Evolution of proton-induced defects in a cryogenically irradiated p-channel CCD

P-channel CCDs have been shown to display improved tolerance to radiation-induced charge transfer inefficiency (CTI) when compared to n-channel CCDs. This is attributed to the properties of the dominant charge-trapping defect species in p-channel silicon relative to the operating conditions of the CCD. However, precise knowledge of defect parameters is required in order to correct for any induced CTI. The method of single trap-pumping allows us to analyse the defect parameters to a degree of accuracy that cannot be achieved with other common defect analysis techniques such as deep-level transient spectroscopy (DLTS). We have analysed using this method the defect distribution in an e2v p-channel CCD204 irradiated with protons at cryogenic temperature (153K). The dominant charge trapping defects at these conditions have been identified as the donor level of the silicon divacancy and the carbon interstitial defect. The defect parameters are analysed both immediately post irradiation and following several subsequent room-temperature anneal phases. The evolution of the defect distribution over time and through each anneal phase provides insight into defect interactions and mobility post-irradiation. The results demonstrate the importance of cryogenic irradiation and annealing studies, with large variations seen in the defect distribution when compared to a device irradiated at room-temperature, which is the current standard procedure for radiation testing

Low Voltage Electron Multiplying CCD in a CMOS Process

Low light level and high-speed image sensors as required for space applications can suffer from a decrease in the signal to noise ratio (SNR) due to the photon-starved environment and limitations of the sensor’s readout noise. The SNR can be increased by the implementation of Time Delay Integration (TDI) as it allows photoelectrons from multiple exposures to be summed in the charge domain with no added noise. Electron Multiplication (EM) can further improve the SNR and lead to an increase in device performance. However, both techniques have traditionally been confined to Charge Coupled Devices (CCD) due to the efficient charge transfer required. With the increase in demand for CMOS sensors with equivalent or superior functionality and performance, this paper presents findings from the characterisation of a low voltage EMCCD in a CMOS process using advanced design features to increase the electron multiplying gain. By using the CMOS process, it is possible to increase chip integration and functionality and achieve higher readout speeds and reduced pixel size. The presented characterisation results include analysis of the photon transfer curve, the dark current, the electron multiplying gain and analysis of the parameters’ dependence on temperature and operating voltage

Fully depleted and backside biased monolithic CMOS image sensor

We are presenting a novel concept for a fully depleted, monolithic, pinned photodiode CMOS image sensor using reverse substrate bias. The principle of operation allows the manufacture of backside illuminated CMOS sensors with active thickness in excess of 100 µm. This helps increase the QE at near-IR and soft X-ray wavelengths, while preserving the excellent characteristics associated with the pinned photodiode sensitive elements. Such sensors are relevant to a wide range of applications, including scientific imaging, astronomy, Earth observation and surveillance. A prototype device with 10 µm and 5.4 µm pixels using this concept has been designed and is being manufactured on a 0.18 µm CMOS image sensor process. Only one additional implantation step has been introduced to the normal manufacturing flow to make this device. The paper discusses the design of the sensor and the challenges that had to be overcome to realise it in practice, and in particular the method of achieving full depletion without parasitic substrate currents. It is expected that this new technology can be competitive with modern backside illuminated thick CCDs for use at visible to near-IR telescopes and synchrotron light sources

Evolution and impact of defects in a p-channel CCD after cryogenic proton-irradiation

P-channel CCDs have been shown to display improved tolerance to radiation-induced charge transfer inefficiency (CTI) when compared to n-channel CCDs. However, the defect distribution formed during irradiation is expected to be temperature dependent due to the differences in lattice energy caused by a temperature change. This has been tested through defect analysis of two p-channel e2v CCD204 devices, one irradiated at room temperature and one at a cryogenic temperature (153K). Analysis is performed using the method of single trap pumping. The dominant charge trapping defects at these conditions have been identified as the donor level of the silicon divacancy and the carbon interstitial defect. The defect parameters are analysed both immediately post irradiation and following several subsequent room-temperature anneal phases up until a cumulative anneal time of approximately 10 months. We have also simulated charge transfer in an irradiated CCD pixel using the defect distribution from both the room-temperature and cryogenic case, to study how the changes affect imaging performance. The results demonstrate the importance of cryogenic irradiation and annealing studies, with large variations seen in the defect distribution when compared to a device irradiated at room-temperature, which is the current standard procedure for radiation-tolerance testing